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3V to 20V - Analog. . . . . . . . . . . . . . . . 2µW (Typ) at VDD -VSS = VDD -VEE = 10V • Binary Address Decoding on Chip • 5V, 10V and 15V Parametric Ratings • 10% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC • Break-Before-Make Switching Eliminates Channel Overlap Applications • Analog and Digital Multiplexing and Demultiplexing • A/D and D/A Conversion • Signal Gating CD4051B, CD4052B, CD4053B Pinouts CD4051B (PDIP, CDIP, SOIC, TSSOP) TOP VIEW 4 1 16 VDD 6 2 15 2 COM OUT/IN 3 14 1 7 4 13 0 CHANNELS IN/OUT CD4052B (PDIP, CDIP, TSSOP) TOP VIEW 0 1 16 VDD 2 2 15 2 COMMON “Y” OUT/IN 3 14 1 Y CHANNELS IN/OUT X CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT Y CHANNELS IN/OUT 3 4 13 COMMON “X” OUT/IN 5 5 12 3 1 5 12 0 INH 6 11 A INH 6 11 3 VEE 7 10 B VEE 7 10 A VSS 8 9 C VSS 8 9 B X CHANNELS IN/OUT CD4053B (PDIP, CDIP, TSSOP) TOP VIEW IN/OUT by 1 16 VDD bx 2 15 OUT/IN bx OR by cy 3 14 OUT/IN ax OR ay OUT/IN CX OR CY 4 13 ay IN/OUT CX 5 12 ax INH 6 11 A VEE 7 10 B VSS 8 9 C IN/OUT Functional Block Diagrams CD4051B CHANNEL IN/OUT 16 VDD 7 6 5 4 3 2 1 0 4 2 5 1 12 15 14 13 TG TG A † 11 TG B † 10 LOGIC LEVEL CONVERSION C † 9 INH † 6 TG BINARY TO 1 OF 8 DECODER WITH INHIBIT 3 TG TG TG TG 8 VSS COMMON OUT/IN 7 VEE † All inputs are protected by standard CMOS protection network.

3V to 20V - Analog. . . . . . . . . . . . . . . . 2µW (Typ) at VDD -VSS = VDD -VEE = 10V • Binary Address Decoding on Chip • 5V, 10V and 15V Parametric Ratings • 10% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC • Break-Before-Make Switching Eliminates Channel Overlap Applications • Analog and Digital Multiplexing and Demultiplexing • A/D and D/A Conversion • Signal Gating CD4051B, CD4052B, CD4053B Pinouts CD4051B (PDIP, CDIP, SOIC, TSSOP) TOP VIEW 4 1 16 VDD 6 2 15 2 COM OUT/IN 3 14 1 7 4 13 0 CHANNELS IN/OUT CD4052B (PDIP, CDIP, TSSOP) TOP VIEW 0 1 16 VDD 2 2 15 2 COMMON “Y” OUT/IN 3 14 1 Y CHANNELS IN/OUT X CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT Y CHANNELS IN/OUT 3 4 13 COMMON “X” OUT/IN 5 5 12 3 1 5 12 0 INH 6 11 A INH 6 11 3 VEE 7 10 B VEE 7 10 A VSS 8 9 C VSS 8 9 B X CHANNELS IN/OUT CD4053B (PDIP, CDIP, TSSOP) TOP VIEW IN/OUT by 1 16 VDD bx 2 15 OUT/IN bx OR by cy 3 14 OUT/IN ax OR ay OUT/IN CX OR CY 4 13 ay IN/OUT CX 5 12 ax INH 6 11 A VEE 7 10 B VSS 8 9 C IN/OUT Functional Block Diagrams CD4051B CHANNEL IN/OUT 16 VDD 7 6 5 4 3 2 1 0 4 2 5 1 12 15 14 13 TG TG A † 11 TG B † 10 LOGIC LEVEL CONVERSION C † 9 INH † 6 TG BINARY TO 1 OF 8 DECODER WITH INHIBIT 3 TG TG TG TG 8 VSS COMMON OUT/IN 7 VEE † All inputs are protected by standard CMOS protection network.

These filters are used to interpolate and reposition luminance and chrominance line to improve picture quality. These filters are capble of generating up to eight, unique subline value between two consecutive scan lines. The generation of lines depends on the ratio between the height of the source image and the target image. In applications where DRAM bandwidth are critical the filters can be configured as simple line-repeating to reduce the DRAM bandwidth required. The Video Processor unit integrates two separate horizontal postprocessing filter, a simple 2-tap linear horizontal filter and an 8-tap programmable filter.

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